Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work

VLSI

Towards a silicon primordial soup: A fast approach to hardware evolution with

A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.

This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future. 1

INTRINSIC EVOLUTION OF ANALOG ELECTRONIC CIRCUITS

Abstract. This paper surveys the research on intrinsic evolution of analog electronic circuits done at the University of Heidelberg. The aims of the project are discussed with reference to the related fields of evolvable hardware and analog design automation. A Field Programmable Transistor Array (FPTA) is used as the substrate for the artificial evolution process. It consists of 16 × 16 transistor cells fabricated in a 0.6 µm CMOS process. Static as well as dynamic properties of the programmable transistor array are estimated by characterization measurements of the chip. The chip is embedded in an evolution system consisting of a PC running the evolutionary algorithm and a PCI card that connects the PC to the FPTA and provides the conversion between digital and analog signals. As case studies the quasi dc behavior of different logic gates as well as a Gaussian output characteristic are evolved.